Tunnel transistors are already known to the person skilled in the art. U.S. Pat. No. 5,365,083 for example describes a tunnel transistor. The tunnel transistor comprises a drain, a source and at least a first gate for controlling current between the drain and the source. The drain comprises a first semiconductor part which is doped with n-type dopants in electrical contact with a drain electrode. The source comprises a second semiconductor part which is doped with p-type dopants in electrical contact with a source electrode. The first gate comprises a first gate dielectric material adjacent to the first semiconductor part along and contacting the first semiconductor part with a first side of the first gate dielectric material at a first side of the tunnel transistor. The first gate also comprises a first gate electrode along the first gate dielectric and opposing the first side of the first gate dielectric material. The drain and the source are positioned adjacently to each other along a p-n junction of the tunnel transistor. The p-n junction extends longitudinally along an extending direction. The tunnel transistor comprises a second gate separate from the first gate. The second gate comprises a second gate dielectric material adjacent to the second semiconductor part along and contacting the second semiconductor part at a second side of the tunnel transistor with a first side of the second gate dielectric material. The second gate also comprises a second gate electrode along the second gate dielectric material and opposing the first side of the second gate dielectric material. The second side of the tunnel transistor opposes the first side of the tunnel transistor. The first and the second gate are provided to control current between a substantially conducting state and a substantially isolating state between the drain and the source by an electrical potential difference between the first and the second gate generating an electric field between the first and the second gate.
However, a substantial part of the first and the second gate electrodes are also positioned along respectively the second and the first semiconductor part. In such a configuration the electric field lines of the electric field generated are substantially parallel to the p-n junction and, although allowing a certain band bend, typically large electrical potential differences will be needed between the gate electrodes in order to deplete or create accumulation of carriers in the semiconductor region between the gates in order to create a band bending which is parallel to the gates, only allowing a limited use, especially for example in the field of logical gates. Without wanting to be bound by any theory, t this is believed to be because the p-n junction is creating a band bending orthogonal to the gates and this band bending has to be made negligible with respect to the gate-induced band bending.
U.S. Pat. Publ. No. 2009-0101975-A1 also describes a tunnel transistor. The tunnel transistor comprises a drain, a source and at least a first and a second gate for controlling current between the drain and the source. Although different gates are provided, the field lines of the electric field generated are either again substantially parallel to the extending direction and/or the first and second gate electrode are not positioned along respectively the first and the second semiconductor part but instead along a channel forming region which is intrinsically conducting or only weakly doped leading still to relatively large electrical potential differences between the gate electrodes.
U.S. Pat. No. 5,021,841 describes a tunnel transistor with a controlled negative differential resistance characteristic.